Advance Physical Design

Gain practical expertise in Advanced Physical Design with Saftech Academy’s intensive weekday program. This offline course provides end-to-end training in the full ASIC flow using industry-standard Synopsys tools, guided by expert trainers with 10+ years of VLSI experience.

Course Details

Start Date

29th September 2025

Duration:

5 Months (Monday–Friday)

Timing

5 Hours per Day

Total Training

500+ Hrs of Practical Learning

Training Mode

Regular Offline Classes

Key Highlights

Full-Time Offline Classroom Training
500+ Hours of Hands-on Practice
Placement, Routing, CTS, Power & Verification covered in depth
Taught by Industry Professionals with proven expertise
Includes Certification upon completion

Eligibility

Advance Physical Design Overview

SAFTECH ACADEMY, we prepare future VLSI engineers to excel in every stage of the semiconductor design process. Our Advanced Physical Design program takes you through the complete ASIC flow—from floor planning to GDSII—using industry-leading Synopsys EDA tools. You will become master in placement, routing, clock tree synthesis, power planning, and sign-off, while learning to create compact, efficient, and reliable IC layouts. We also emphasize verification skills to ensure your designs meet the highest standards of performance, power, and reliability through rigorous checks like signal integrity, power integrity, and timing analysis. With hands-on training guided by expert engineers, you will gain the expertise to deliver high-performance, power-efficient chips for today’s competitive semiconductor industry.

Advance Physical Design Course Key Features

Instructor led Live Offline Classes
Integrated labs to give you hands-on experience
Simulation test at the end of each topic to get you job-ready
Industry-recognized course completion certificate from SAFTECH ACADEMY
Covers 2-3 Capstone Projects required to become aPhysical DesignProfessional
Hands-on based learning

Skills Covered

Benefits

Annual Salary

4LP, 6.5LPA, 9LPA

Hiring

Annual Salary

6LPA,9.5LPA,14LPA

Hiring

EDA Tools Covered

VCS for Digital Design
Design Compiler for Synthesis
PrimeTime for STA
IC Compiler II (ICC2) for NET-GJS Flow
StarRC for Extraction
IC Validator for Physical Verification

Pre-Requisites

Educational Background of Engineering
Basic Digital Electronics
Familiarity with VLSI Basics
Fundamentals of Electronics Devices
Problem-Solving Skills
Comfort with Computers

Course Content

Topic 1: Linux

Introduction to Linux,Command-Line Operators, File Management, Process Handling, Text Editors, Text Manipulation, Network Operations, Special Keystrokes and GVIM.

Topic 2: Digital Design

1. Number Systems and Logic Basics
Number Systems
Boolean Algebra
SOP (Sum of Products) and POS (Product of Sums) Forms
Karnaugh Maps for Logic Simplification

2. Digital Circuit Design
Combinational Circuits
Sequential Circuits
Finite State Machines (FSMs)

3. Timing and Performance
Frequency Division Techniques
Setup and Hold Time Analysis

4. Advanced Design Considerations
Metastability
Noise Margins
Power Considerations
Fanout Limitations
Timing Constraints
FIFO Depth Calculation

Topic 3: CMOS Device Architecture and Technology

1. Basic Electronic Components
Electronic Devices Overview
Power Sources
Thevenin’s Theorem
Norton’s Theorem

2. Semiconductor Device Physics
Atomic Structure and Electronic Configuration
Semiconductor Doping
Diodes – Biasing Techniques
V-I Characteristics of Diodes

3. MOSFET Fundamentals
MOSFET Regions of Operation
V-I Characteristics of MOSFETs

4. CMOS Design Principles
CMOS Function Implementation
Stick Diagram Representation
Layout Design Techniques

5. Second-Order Effects in MOS Devices
Body Effect
Channel Length Modulation
Punch-Through Effect
Subthreshold Conduction
Drain-Induced Barrier Lowering (DIBL)

6. Semiconductor Process Technology
Clean Room Standards and Practices
Wafer Manufacturing Process
Oxidation Techniques
Diffusion Processes
Ion Implantation Methods
Lithography Techniques

Topic 4: Verilog

1. Introduction to Verilog
Overview of Verilog HDL
Applications and Use Cases of Verilog in Digital Design

2. Verilog Language Concepts
Verilog Language Basics and Constructs
Data Types – Nets, Registers, and Arrays

3. Verilog Operators
Logical Operators
Bitwise and Reduction Operators
Concatenation and Conditional Operators
Relational and Arithmetic Operators
Shift and Equality Operators
Operator Precedence Rules

4. Assignment Types in Verilog
Continuous Assignments
Procedural Assignments – Inter/Intra Assignment Delays
Blocking and Non-Blocking Assignments

5. Control and Functional Constructs
Execution Branching Statements
Tasks and Functions

6. Finite State Machines (FSM) in Verilog
Basic FSM Structure
Moore vs. Mealy FSM Models
Common FSM Coding Styles
Registered Output Implementation

Topic 5: ASIC Design Flow & Synthesis

1. Overview of ASIC Design Flow
Introduction to the ASIC Design Process
Role and Importance of Synthesis in the Flow

2. Synthesis Process
Synthesis Flow and Key Stages
Writing Timing Constraints in SDC Format
Applying Constraints for Timing, Power, and Area Targets
Optimization Techniques for Design Goals

3. Design Synthesis Execution
Running the Synthesis Process
Generating and Analysing Synthesis Reports
Saving the Netlist and Associated SDC Files

Topic 6: LEC (Logic Equivalence Check)

1. Introduction to Formal Verification
Overview and Importance of Formal Verification in Design Flow

2. Verification Process
Understanding and Matching Compare Points
Debugging Non-Equivalent Points

3. Advanced Analysis
Performing What-If Analysis

Topic 7: Intro to PD, Sanity Checks & Data Preparation

1. Introduction to Physical Design
Overview of Physical Design in VLSI
Physical Design Flow and Key Stages

2. Data Preparation for Physical Design
Required Input Files for PD:
Netlist
SDC (Synopsys Design Constraints)
Libraries
Technology Files
TLU+ Files

Contents and Purpose of Each Input File

Topic 8: Floor Planning in Physical Design

1. Introduction to Floor planning
Purpose and Goals of Floor planning
Sanity Checks Before Floor planning

2. Floor planning Concepts
Key Aspects of Floor planning
Rectangular and Rectilinear Floor Plan Approaches

3. Floor planning Calculations
Die Size Estimation – Core Utilization and Aspect Ratio
I/O Placement Strategies
Macro Placement Guidelines
Channel Width Estimation

Topic 9: Routing in Physical Design

1. Introduction to Power Routing
Goals and Importance of Power Routing
Power Distribution Structures – Rings, Straps, Follow-Pins, and Standard Cell Rails

2. Power Planning Essentials
Understanding Metal Stack Information
Power Planning Methodology

3. Power Integrity and Analysis
IR Drop Analysis
Types of Power Consumption
Electromigration Analysis

4. Low-Power Design
Importance of Low-Power Design
Low-Power Design Techniques

Topic 10: Placement in Physical Design

1. Introduction to Placement
Goals and Objectives of Placement
Types of Placement Strategies

2. Pre-Placement Activities
End-Cap Cell Insertion
Tap Cell Placement
I/O Buffer Placement

3. Placement Optimization and Analysis
Placement Optimization Techniques
Congestion Analysis
Timing Analysis During Placement

4. Special Cells and Net Handling
Tie-Cell Insertion
High-Fanout Net Synthesis (HFNS)

5. Design-for-Test (DFT) Considerations
Scan Chain Reordering

6. Path and Region Management
Path Grouping
Creating Bounds for Critical Regions

Topic 11: Static Timing Analysis (STA)

1. Introduction to STA
Overview and Key Concepts of Static Timing Analysis

2. Timing Fundamentals
Basic Timing Checks – Setup and Hold
Understanding and Writing Timing Constraints (SDC)
Timing Corners and Their Significance

3. Timing Analysis and Optimization
Timing Report Analysis
General Optimization Techniques
Common Causes of Timing Violations
Strategies for Fixing Timing Violations

4. Pre-CTS Timing Optimization
Pre-Clock Tree Synthesis (CTS) Optimization for Setup Violation Fixes

Topic 12: CTS (Clock Tree Synthesis)

1. Introduction to CTS
Goals and Objectives of Clock Tree Synthesis
Types of Clock Trees

2. CTS Preparation
Constraints for Clock Tree Synthesis

3. Clock Tree Implementation
Building the Clock Tree
Analyzing CTS Results

4. Post-CTS Optimization
Fixing Setup Violations
Fixing Hold Violations

Topic 13: Routing in Physical Design

1. Introduction to Routing
Goals and Objectives of Routing

2. Stages of Routing
Global Routing
Track Assignment
Detailed Routing

3. Routing Strategies and Options
Available Routing Options and Techniques

4. Routing Verification and Fixes
Fixing Routing Violations – DRC and LVS

5. Post-Route Optimization
Timing and Congestion Improvements After Routing

6. Routing Challenges and Best Practices
Common Issues in Routing
Guidelines for Achieving Optimum Routing Results

Topic 14: Post-Layout Static Timing Analysis

1. Post-Layout STA Fundamentals
Post-Layout STA Using SPEF (Standard Parasitic Exchange Format)
Multi-Mode Multi-Corner (MMMC) STA

2. Variation and Derating Considerations
Derating Factors in Timing Analysis
PVT (Process, Voltage, Temperature) Variations
OCV (On-Chip Variation) Effects

3. Signal Integrity Analysis
Crosstalk Analysis and Its Impact on Timing

Topic 15: Engineering Change Order (ECO) in Physical Design

1. Introduction to ECO
Definition and Purpose of ECO in VLSI Design

2. Types of ECO
Timing ECO
Functional ECO

3. ECO Implementation
Performing ECO Placement
Performing ECO Routing

Topic 16: Physical Verification and Sign-Off

1. Physical Verification
Design Rule Check (DRC)
Layout Versus Schematic (LVS)

2. Power Integrity Checks
IR Drop Analysis

3. Reliability Checks
Electromigration Analysis

Topic 17: Project

Participants will work on projects covering the complete Netlist-to-GDSII flow, replicating real-world block-level Physical Design processes. These projects will focus on achieving minimum area, low power consumption, and high performance.

The execution methodology will mirror typical industry block-level implementation, where students will receive a block-level input database and will be required to deliver a final GDSII after resolving all issues identified during sign-off checks.

Why to Join Advance Physical Design Course

By the end of the program, you will have the confidence and practical expertise to handle real-world Physical Design challenges and deliver a design that meets timing, power, and area targets—just like in the VLSI industry.

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Mon-Fri

10AM to 7PM

Sat-Sun

08AM to 2PM

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