Design for Testability (DFT)

Master the art of Design for Testability with Saftech Academy’s intensive weekend program. This offline course provides complete hands-on training in the DFT flow using industry-standard Synopsys tools, guided by expert trainers with 10+ years of VLSI experience.

Course Details

Start Date

TBD

Duration:

16 Weekends (Saturday & Sunday)

Timing

5 Hours per Day

Total Training

120+ Hrs of Practical Learning

Training Mode

Weekends Offline Classes

Key Highlights

Weekend Offline Classroom Training
500+ Hours of Hands-on Practice
Comprehensive Coverage: Scan Insertion, ATPG, Fault Simulation & Debug
Learn directly from Experienced Industry Professionals
Certification Provided upon Completion

Eligibility

Advance DFT (Design for Testability) Overview

SAFTECH ACADEMY, we prepare future VLSI engineers to excel in every stage of chip testability. Our Advanced DFT program takes you through the complete design-for-test flow—covering scan architecture, scan insertion, ATPG, BIST, compression, and at-speed testing—using industry-leading Synopsys EDA tools. You will master fault modelling, pattern generation, and test coverage improvement, while learning how to debug and optimize designs for efficiency and reliability.

With hands-on training and real-world projects guided by expert engineers, you will gain the expertise to deliver high-quality, test-ready chips for today’s competitive semiconductor industry.

Advance DFT Course Key Features

Instructor led Live Offline Classes
Integrated labs to give you hands-on experience
Simulation test at the end of each topic to get you job-ready
Industry-recognized course completion certificate from SAFTECH ACADEMY
Covers 1-2 Capstone Projects required to become a DFT Professional
Hands-on based learning

Skills Covered

Fundamental of Linux
Digital Design
Scan Architecture and Scan Insertion
ATPG & Fault Modelling
BIST (Built-In Self-Test) Techniques
Compression & At-Speed Testing
Debugging, Simulation, and Coverage Improvement
Capstone Projects

Benefits

Annual Salary

5LP, 9.5LPA, 12LPA

Hiring

Annual Salary

7.5LPA,12LPA,16.5LPA

Hiring

EDA Tools Covered

Pre-Requisites

Educational Background of Engineering
Basic Digital Electronics
Familiarity with VLSI Basics
Fundamentals of Electronics Devices
Problem-Solving Skills
Comfort with Computers

Course Content

Topic 1: Linux

Introduction to Linux, Command-Line Operators, File Management, Process Handling, Text Editors, Text Manipulation, Network Operations, Special Keystrokes and GVIM.

Topic 2: Digital Design

1. Number Systems and Logic Basics
Number Systems
Boolean Algebra
SOP (Sum of Products) and POS (Product of Sums) Forms
Karnaugh Maps for Logic Simplification

2. Digital Circuit Design
Combinational Circuits
Sequential Circuits
Finite State Machines (FSMs)

3. Timing and Performance
Frequency Division Techniques
Setup and Hold Time Analysis

4. Advanced Design Considerations
Metastability
Noise Margins
Power Considerations
Fanout Limitations
Timing Constraints
FIFO Depth Calculation

Topic 3: CMOS Device Architecture and Technology

1. Basic Electronic Components
Electronic Devices Overview
Power Sources
Thevenin’s Theorem
Norton’s Theorem

2. Semiconductor Device Physics
Atomic Structure and Electronic Configuration
Semiconductor Doping
Diodes – Biasing Techniques
V-I Characteristics of Diodes

3. MOSFET Fundamentals
MOSFET Regions of Operation
V-I Characteristics of MOSFETs

4. CMOS Design Principles
CMOS Function Implementation
Stick Diagram Representation
Layout Design Techniques

5. Second-Order Effects in MOS Devices
Body Effect
Channel Length Modulation
Punch-Through Effect
Subthreshold Conduction
Drain-Induced Barrier Lowering (DIBL)

6. Semiconductor Process Technology
Clean Room Standards and Practices
Wafer Manufacturing Process
Oxidation Techniques
Diffusion Processes
Ion Implantation Methods
Lithography Techniques

Topic 4: Verilog

1. Introduction to Verilog
Introduction to Verilog HDL
Overview of Digital Design with Verilog

2. Hierarchical Modeling Concepts
Top-Down Design Methodology
Bottom-Up Design Methodology
Modules and Their Structure
Components of Simulation
Stimulus Block

3. Modeling Styles in Verilog
Behavioral (Algorithmic) Modeling
Dataflow Modeling
Gate-Level Modeling
Switch-Level Modeling

4. Basic Language Concepts
Lexical Conventions
Operators in Verilog
Data Types
System Tasks
Compiler Directives
File Input and Output

5. Modules and Ports
Module Definition
Port Declaration
Connecting Ports
Hierarchical Name Referencing

6. BehavioralModeling in Depth
Initial and Always Blocks
Blocking and Non-Blocking Statements
Delay Control and Event Control
Conditional Statements and Loops
Sequential and Parallel Blocks

Topic 5: Introduction to DFT and Testing Fundamental

1. ASIC Flow
Overview of the ASIC Design Flow
Stages from RTL to GDSII

2. Design for Testability (DFT) Basics
Importance of DFT in ASIC Design
Common DFT Techniques

3. Chip Fabrication Process
Wafer Fabrication Steps
Packaging and Testing

4. Automatic Test Equipment (ATE) Basics
Role of ATE in Chip Validation
Fundamentals of ATE Operation

Topic 6: SCAN Insertion

1. Introduction to Scan Insertion
Overview of Scan Architecture in VLSI
Role of Scan in Design for Testability (DFT)

2. Scan Design Basics
Fundamentals of Scan Design
Benefits and Limitations

2. Scan Design Guidelines
Scan Golden Rules
Scan DRC (Design Rule Check)

4. Scan Insertion and Validation
Scan Insertion Process
Generating and Understanding Test Protocols
5. Advanced Scan Concepts
Lock-Up Latches and Their Usage in Scan Chains

Topic 7: SCAN Compression

1. Introduction to Test Compression
Basics of Test Compression
Need for Compression in VLSI Testing

2. Compression Techniques
Common Test Compression Methods
Trade-offs Between Area, Power, and Test Time

3. On-Chip Clocking
Concept of On-Chip Clocking for Test
Implementation Approaches

4. At-Speed Testing
Importance of At-Speed Testing
Techniques and Challenges in At-Speed Testing

Topic 8: Scan Architectures

1. Hierarchical Scan
Concept and Need for Hierarchical Scan
Advantages in Large SoC Designs

2. Boundary Scan (BScan)
Fundamentals of Boundary Scan Architecture
Applications in Board-Level Testing

3. JTAG (Joint Test Action Group)
Overview of JTAG Standard (IEEE 1149.1)
JTAG Instructions and Operation
Role of JTAG in Debug and Testing

Topic 9: Introduction to ATPG and Fundamental

1. ATPG Fundamentals
Introduction to ATPG
Basics of Fault Models

2. Fault Modeling and Reduction
Fault Collapsing Techniques
Impact on Test Efficiency

3. ATPG Algorithms
Common ATPG Algorithms
Deterministic vs. Random Pattern Generation
Trade-offs in Fault Coverage, Area, and Test Time

Topic 10: Fault Modeling and Test Modes

1. Fault Models
Stuck-at Fault Model
Transition Fault Model
Path Delay Faults
Bridging and Other Advanced Fault Models

2. ATPG DRC (Design Rule Checks)
Importance of ATPG DRC
Common Violations and Fixes

3. Fault Classes
Testable Faults
Redundant Faults
Untestable Faults

4. ATPG Modes
Deterministic ATPG
Random ATPG
Hybrid ATPG Modes

Topic 11: Simulation & Pattern Generation

1. Simulation Basics
Role of Simulation in ATPG
Pre- and Post-ATPG Simulation Flow

2. ATPG Simulations
Fault Simulation Techniques
Pattern Application and Validation
Debugging Simulation Failures

3. Coverage Improvement
Understanding Test Coverage Metrics
Identifying Coverage Gaps
Techniques for Improving Fault Coverage
Balancing Coverage, Area, and Test Time

Topic 12: At-Speed Testing with ATPG

1. At-Speed ATPG
Need for At-Speed Testing
Transition Delay Faults
Path Delay Faults
Challenges in At-Speed Pattern Generation

2. Launch Techniques (LOC vs LOS)
LOC (Launch on Capture) – Methodology, Advantages, Limitations
LOS (Launch on Shift) – Methodology, Advantages, Limitations
Comparison: LOC vs LOS

3. At-Speed Simulations
Simulation Setup for At-Speed Patterns
Debugging At-Speed Failures
Coverage Analysis for Delay Faults
Industry Best Practices in At-Speed Testing

Topic 13: Scan Debug, Diagnosis & Fault Simulation

1. Scan Simulations & Debugging
Role of Scan Simulations in DFT
Common Scan Simulation Issues
Debugging Techniques for Scan Chain Failures
Ensuring Correctness of Scan Insertion

2. Diagnosis Flow
Introduction to Fault Diagnosis
Failure Data Collection and Analysis
Diagnosis Algorithms & Flow
Root Cause Identification in Silicon Debug

3. Fault Simulation
Fault Simulation Basics
Types of Fault Simulation (Serial, Parallel, Differential)
Fault Coverage Estimation
Fault Simulation for Test Quality Improvement

Topic 14: BIST

BIST Architecture
Memory BIST
Logic BIST

Topic 15: Project

Capstone Project: Block-Level DFT Implementation
As part of the program, participants will work on a realistic block-level design project that simulates industry workflows. The project includes:

Analyzing& fixing DRC violations to ensure design rule compliance.
Scan Chain Stitching – implementing scan insertion both with and without scan compression.
ATPG Pattern Generation – creating test patterns for multiple fault models.
Pattern Simulation – verifying the correctness of ATPG patterns through simulations.
Test Coverage Optimization – applying advanced techniques to further improve fault coverage.

This hands-on project enables participants to gain practical expertise in DFT methodologies, preparing them for real-world challenges in VLSI design and testing.

Why to Join Advance Physical Design Course

By the end of the program, you will have the confidence and practical expertise to handle real-world DFT challenges and deliver a design that meet SCAN Insertions & ATPG Stimulation - just like in the VLSI industry.

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10AM to 7PM

Sat-Sun

08AM to 2PM

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